The technical field of this invention is test access ports for integrated circuits and more particularly a manner to integrate core logic modules each having a test access port.
Continuous decrease in feature size of transistors has led to the recent trend of core-based design. Today""s integrated circuit (IC) becomes tomorrow""s integratable core. Today""s printed circuit board becomes tomorrow""s IC. This decrease in feature size leads to the availability of unprecedented number of transistors on an integrated circuit. Current technology trends lead to projections of further rise in the number of transistors that may be integrated into a single IC. This expected trend in IC technology is leading to a re-prioritization of design issues. The traditional concern of gate/transistor count is becoming relatively less important. Issues like re-usability of existing designs, and minimization of design cycle time, are increasing continuously in importance. A major design problem for large integrated circuits is testability. Moreover, both the recurring and non-recurring test costs of such complex products now constitute a significant fraction of the total cost of the product. It is now likely that a single large IC will employ one or more preexisting cores. Currently the most widely accepted test standard for integrated circuits is IEEE Standard 1149.1, also known as JTAG. This standard was created with the primary goal of alleviating board-test problem via Test Access Ports (TAPs). The JTAG standard cannot be directly used in IC""s containing cores which already include Test Access Ports. At the same time, widespread acceptance of JTAG in the electronics and semiconductor industry requires current and future IC""s to be fully compliant with this standard. Thus there is a great need to develop a test access mechanism that allows embedded cores and non-core logic in an IC to be accessed via a well-defined JTAG interface.
Recently, some solutions have been proposed to address this problem that either violate the JTAG standard, or require modification of the TAP in existing cores, or follow a completely different Built-In Self Test (BIST) based technique to testing embedded cores, without addressing the issue of JTAG compliant test access to the embedded cores.
This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a first test access port, preferrably compliant with the IEEE Standard 1149.1 commonly known as JTAG. The electronic circuit includes at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. The test access port controller is preferrably also JTAG compliant. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can control the programmable switch to regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states. This may occur upon detection of a wake-up instruction loaded into a snoopy instruction register during a snoopy state corresponding to an instruction input state. Alternatively, a count of instruction bits more than the most bits for instruction input for any embedded core can trigger the wake-up function.